As electronic equipment has been reduced in size, thickness, and weight in recent years, high-density packaging for semiconductor devices has been in increasing demand. Further, as semiconductor elements have been mounted with higher densities with advances in micromachining technology, so-called chip packaging technology has been proposed to directly mount chip-size packages or semiconductor elements of bare chips.
For example, the prior art of a semiconductor device includes an element structure and a method of manufacturing the same in which a transparent plate is bonded on an image pickup region of a semiconductor element with an adhesive in a semiconductor image pickup device and the thickness of the semiconductor image pickup device is reduced with lower cost (for example, see WO2005/022631).
In this method, as shown in FIG. 3, a protective member 24 made of glass and so on is secured with an adhesive 23 on a semiconductor element 22 having an image pickup region 21 thereon, through holes 26 are formed directly under electrodes 25 of the semiconductor element 22, and an insulating layer 27 is formed on the inner walls of the through holes 26 and the underside of the semiconductor element 22. After that, the electrodes 25 and external electrodes 30 formed on the underside of the semiconductor element 22 are electrically connected to each other via conductor layers 28, so that the semiconductor image pickup device is obtained. Thus the external size of the semiconductor image pickup device can be as small as a so-called chip size, like the semiconductor element 22.
In the semiconductor device of the prior art, however, the through holes are formed on the semiconductor element by dry etching such as plasma etching and RIE and a semiconductor wafer has a large thickness of about 50 μm to 200 μm. Such deep etching requires a long time in a manufacturing process, increasing the cost of a product.
Since the through holes have a large aspect ratio, the insulating film becomes thin at the bottoms of the through holes when the insulating film is formed in the through holes in a process after the through holes are formed. Further, when the conductor layer is formed in the through holes by plating, a plating solution hardly enters near the bottoms of the through holes and the conductor layer is unevenly formed, so that desired electrical characteristics cannot be obtained for the product and the yield is reduced. Consequently, the cost of the product is similarly increased.